发明名称 NAND flash memory with erase verify based on shorter delay before sensing
摘要 <p>A non-volatile memory device (100) is proposed. The non-volatile memory device includes a plurality of memory cells (110) each one having a programmable threshold voltage, and means for reading (130, 140, 150) a set of selected memory cells with respect to a plurality of reference voltages, for each selected memory cell the means for reading including means for charging (Pc) a reading node (BL) associated with the selected memory cell with a charging voltage (Vc), means for biasing (130) the selected memory cell with a biasing voltage, means for connecting (120d, 120s) the charged reading node with the biased selected memory cell, and means for sensing (205) a voltage at the reading node after a predefined delay from the connection, for at least a first one of the reference voltages (V R ) the biasing voltage being a first biasing voltage equal to the first reference voltage and the delay being a common first delay (Te), wherein for at least a second one of the reference voltages (Vga) the biasing voltage is a second biasing voltage (V R ) different from the second reference voltage, and the delay is a second delay (Teg) different from the first delay.</p>
申请公布号 EP1752989(A1) 申请公布日期 2007.02.14
申请号 EP20050106976 申请日期 2005.07.28
申请人 STMICROELECTRONICS S.R.L.;HYNIX SEMICONDUCTOR INC. 发明人 BOVINO, ANGELO;MICHELONI, RINO;RAVASIO, ROBERTO
分类号 G11C16/34;G11C16/32;G11C16/26 主分类号 G11C16/34
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