Clock signal control method and circuit and data transmitting apparatus employing the same

摘要

A control circuit for clock signals which enables phase errors of respective clock signals to be averaged out as the phase difference between clock signals is kept. Multi-phase clock signals are interacted to average out respective phase error components between respective phases. To this end, plural stages of the averaging circuits for averaging out errors of respective phases are provided and clock signals are passed through the averaging circuits to effect averaging progressively to average out the phase errors for the entire clock signals.