| 摘要 |
<p>Combination circuitry for combining a plurality of multi-bit partial product terms, comprising at least one stage arranged to receive a first number of input bits, wherein at least one stage comprises at least one combiner comprising; a first logic device comprising; an input arranged to receive a first set of the first number of input bits and an output arranged to output a first combined result a second logic device comprising a first input arranged to receive a second set of the first number of input bits, a second input connected to receive the first combined result, a first output arranged to output a second combined result and a second output arranged to output a first combined bit group; and a third logic device comprising an input connected to receive the second combined result and an output arranged to output a second combined bit group, whereby the first combined bit group is available for a further stage of the combination circuitry before the second combined bit group.</p> |
