| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device in which the scale of a memory capacity can be enlarged while power consumption at standby time and operation time is reduced. <P>SOLUTION: A memory cell array 110 is provided with source wires SN0 to SNk in the portion of one source wire to memory cells for two lines adjacent to each other. Moreover, a plurality of source bias control circuits 121 which supply source bias potentials higher than a ground potential and lower than a power source potential to the respective source wires are provided corresponding to the respective source wires. In a standby period, the source bias control circuits 121 control the respective source wires to be in a state where the source bias potentials are supplied. In an active period, the source bias control circuits 121 control source wires which are not connected with memory cells to be read to be in a state where the source bias potentials are supplied. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
