| 摘要 |
PROBLEM TO BE SOLVED: To provide an excellent memory controller for achieving cost reduction by reducing the number of terminals, writing in the arbitrary address of an SDRAM and memory access by suppressing the deterioration of performance. SOLUTION: An MAD (15:0) terminal sharing an address terminal and at least one portion of a data terminal is installed so as to be used by time-division. Also, a write column address generator 202 is installed for generating a write address for performing write access through the MAD (15:0) terminal to an SDRAM when requesting write access. Furthermore, a terminal(MA10 terminal) to be used when issuing a precharge command to the SDRAM is not shared with the data terminal. Then, a sequencer 201 and selectors 203 to 205 issue a precharge command to the SDRAM by using the MA10 terminal after the lapse of a predetermined time since issuing a read command for executing read access to the SDRAM. COPYRIGHT: (C)2007,JPO&INPIT
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