| 摘要 |
PROBLEM TO BE SOLVED: To achieve power-saving of a PRML (Partial Response Maximum Likelihood) signal processing circuit in which power consumption is a problem. SOLUTION: A frequency detector 113 detects a frequency error between the frequency of a reproduction signal provided from an A/D converter 105 and the frequency of a conversion clock. A phase comparator 112 detects a phase error between an ideal sampling phase of the reproduction signal provided from the A/D converter 105 and the phase of the conversion clock. A loop filter 114 controls the oscillation frequency of a voltage control oscillator 115 based on the frequency error and the phase error. An adaptive equalizer 118 performs waveform equalization of the reproduction signal provided from the A/D converter 105 so as to be a response of a predetermined PR class. A viterbi decoder 110 decodes a waveform-equalized signal to binary data by estimation of a maximum likelihood column. When the frequency error is larger than a designated error, a clock supply control circuit 117 stops clocks to the phase comparator 112, the adaptive equalizer 118 and the viterbi decoder 110 at least. COPYRIGHT: (C)2007,JPO&INPIT
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