发明名称 |
ONE-TRANSISTOR TYPE DRAM TYPE MEMORY CELL, MANUFACTURING METHOD THEREOF AND INTEGRATE CIRCUIT |
摘要 |
<P>PROBLEM TO BE SOLVED: To improve reading sensitivity in a memory cell having one MOS transistor formed in a floating body area whose lower surface is insulated by bonding. <P>SOLUTION: An area 41 having the same conductive type as the floating body area 1 and doped at density higher than the floating body area 1 is arranged under a drain area 10 of the MOS transistor. Consequently effective channel width between a source 9 and the drain 10 is increased, and thereby a reading current to a fixed gate voltage is reduced. <P>COPYRIGHT: (C)2007,JPO&INPIT |
申请公布号 |
JP2007036257(A) |
申请公布日期 |
2007.02.08 |
申请号 |
JP20060203309 |
申请日期 |
2006.07.26 |
申请人 |
STMICROELECTRONICS CROLLES 2 SAS |
发明人 |
VILLARET ALEXANDRE;MAZOYER PASCALE;RANICA ROSSELLA |
分类号 |
H01L21/8242;H01L27/108 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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