| 摘要 |
PROBLEM TO BE SOLVED: To provide a pipeline processor capable of improving reliability without increasing complexity. SOLUTION: This processor comprises an instruction decode unit 401a decoding a fetched instruction and selectively issuing either a core instruction with a fixed instruction execution cycles or an extension instruction defined by a user; a core instruction execution unit 40 executing the issued core instruction; an extension instruction execution unit 402a executing the issued extension instruction; and a reorder buffer 406a temporarily storing the respective instruction results of the core instruction execution unit 40 and the extension instruction execution unit 401a and rearranging and outputting the instruction execution results in the issuing order of the core instruction and the extension instruction. COPYRIGHT: (C)2007,JPO&INPIT
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