| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock reproduction circuit which prevents bit deviation caused by disturbance. <P>SOLUTION: A clock reproduction circuit comprises: a detection clock frequency divider 3 which divides a frequency of a detection clock that extracts phase information of a detection waveform, into 1/N when a certain integer of 2 or more is defined as N; a controlled oscillator frequency divider 4 which divides a frequency of an oscillation clock outputted from a controlled oscillator 2 into 1/(M*N) when an arbitrary positive integer is defined as M; and a reproduction clock frequency divider 5 which divides a frequency of an oscillation clock outputted from the controlled oscillator 2 into 1/M. One input of a phase comparator 1 is an output of the detection clock frequency divider 3, and another output of the phase comparator 1 is an output of the controlled oscillator frequency divider 4. The phase comparator 1 compares a phase of the detection clock frequency-divided into 1/N with that of the oscillation clock frequency-divided into 1/(M*N). The controlled oscillator 2 controls an oscillation frequency based on a result obtained by comparing the phase of the detection clock frequency-divided into 1/N with that of the oscillation clock frequency-divided into 1/(M*N), and an output of the reproduction clock frequency divider 5 is defined as a reproduction clock. <P>COPYRIGHT: (C)2007,JPO&INPIT |
