SERIAL/PARALLEL CONVERSION, PARALLEL/SERIAL CONVERSION, AND FIFO INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a serial/parallel conversion, parallel/serial conversion and FIFO integrated circuit in which circuit scale is reduced and which is capable of dealing with high-speed performance.

SOLUTION: The present invention comprises: a register 1 which inputs serial data 11, converts the serial data into parallel data and outputs them based on a fractional multi-phase clock signal 13 from a counter 3; a selector 2 which receives parallel data 15 from the register 1 and selects one of the data according to a control signal 14; and a counter 4 which generates the control signal to the selector 2 so as to sequentially output data in series from the selector 2 in accordance with the order of inputting the serial data 11 to the register 1.

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