| 摘要 |
An interfacing device ( 23 ) of the type enabling one-way interfacing between a master unit ( 21 ) and a slave unit ( 22 ), includes: a memory plane managed according to a "first in, first out" mode, with write and read pointers, and making it possible to store words coming from the master unit, via an input bus (FIFODin); a bank of output registers capable of containing words read in the memory plane and providing an output signal (FIFODout) capable of being read by the slave unit; a mechanism configured to receive read requests (FIFORdRq=1) coming from the slave unit and write requests (FIFOWr=1) coming from the master unit, each read request requiring the reading of a word group. The interfacing device further includes: a mechanism configured to receive, for each read request, of the size (NbWords) of the word group associated with said read request, size being variable from one read request to the other; and a mechanism configured to acknowledge read requests, generating, for each read request, an acknowledgement signal with a "true" value (FIFORdAck=1) if a number of words at least equal to the size (NbWords) of the word group associated with read request is available on the output signal (FIFODout) of the bank of output registers.
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