发明名称 |
CACHE ARCHITECTURE FOR A PROCESSING UNIT PROVIDING REDUCED POWER CONSUMPTION IN CACHE OPERATION |
摘要 |
<p>A cache memory processing system is disclosed that is coupled to a main memory and a processing unit. The cache memory processing system includes an input, a low order bit data path, a high order bit data path and an output. The input is for receiving input data that includes at least one low order input bit and at least one high order input bit. The low order bit data path is for processing the at least one low order input bit and providing at least one low order output bit. The high order bit data path for processing the at least one high order input bit and providing at least one high order output bit. The high order bit data path includes at least one exclusive or gate. The output is for providing the at least one low order output bit and the at least one high order output bit.</p> |
申请公布号 |
WO2007016491(A2) |
申请公布日期 |
2007.02.08 |
申请号 |
WO2006US29747 |
申请日期 |
2006.07.28 |
申请人 |
THE BOARD OF GOVERNORS FOR HIGHER EDUCATION, STATE OF RHODE ISLAND AND PROVIDENCE PLANTATIONS;YANG, QING |
发明人 |
YANG, QING |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|