发明名称 |
Instruction prefetch unit |
摘要 |
<p>A prefetch buffer is described which supports a computer system having a plurality of different instruction modes. The number of storage locations which are read out of the prefetch buffer during each machine cycle is controlled in dependence on the instruction mode. Thus the prefetch buffer allows a number of different instruction modes to be supported and hides memory access latency. <IMAGE></p> |
申请公布号 |
EP1050802(B1) |
申请公布日期 |
2007.02.07 |
申请号 |
EP19990410052 |
申请日期 |
1999.05.03 |
申请人 |
STMICROELECTRONICS S.A. |
发明人 |
WOJCIESZAK, LAURENT;COFLER, ANDREW |
分类号 |
G06F9/38;G06F9/30;G06F9/318 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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