| 摘要 |
A DLL system includes a phase detector coupled to an input signal for generating a first phase error signal according to the input signal and a clock signal; an up-down counter coupled to the phase detector for generating a counting signal according to the first phase error signal; a sigma-delta modulator (SDM) coupled to the up-down counter for generating a second phase error signal according to the counting signal; an adder coupled to the SDM and the phase detector for summing the first phase error signal and the second phase error signal to generate a sum signal; a clock generator for generating a plurality of candidate clock signals according to a reference clock; and a multiplexer coupled to the clock generator and the phase detector for selecting one of the candidate clock signals to be the clock signal inputted into the phase detector according to the sum signal.
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