| 摘要 |
An integrated circuit provided with a power down and power up mechanism which operates by storing state data including at least architectural state data within storage cells having their own power supply with the main power supply being removed during the power down mode. Prior to removing the main power supply execution of data processing instructions within the instruction pipeline preceding a restart instruction are completed so as to reduce the amount of state data which needs to be stored across the power down event. Thus, a compromise is achieved between rapid power down through the use of dedicated storage cells and the circuit area requirements of such storage cells and the need to complete execution of some partially executed data processor instructions within the instruction pipeline and other operations such as, pending writes within the integrated circuit. The trigger event to trigger power down or power up may be a signal on an external pin, an internally generated signal within the integrated circuit execution of a specific data processing instruction, or other events.
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