发明名称 METHOD AND APPARATUS FOR VERTICALLY LOCKING INPUT AND OUTPUTSIGNALS
摘要 This invention describes a method and apparatus for vertically locking input and output video frame rates. The output vertical sync pulse is locked in phase with the input vertical sync pulse, regardless of the input format and frequency. The output resolution, horizontal refresh rate, and delay are all user selectabl e. Two Phase Locked Loops are connected in series to achive vertical lock between the input and output frames. Locking the vertic al sync pulses between the input and output frames will eliminate mixing of pixels from different input frames in one output frame. The first Phase Locked Loop generates the output pixel clock required to satisfy the user's display preferences but may not precise ly represent the desired output pixel clock required for frame locking because current Phase Locked Loops use integer dividers. A second Phase Locked Loop adjusts its output, which is the reference frequency to the first Phase Locked Loop, until a lock is achieved.
申请公布号 CA2388977(C) 申请公布日期 2007.02.06
申请号 CA20002388977 申请日期 2000.12.29
申请人 RGB SYSTEMS, INC. 发明人 TARACI, BRIAN RICHARD;TROUNG, DUY DUC
分类号 G09G5/12;H04N5/04;G09G5/00;G09G5/18;G09G5/391;H03L7/23;H04N5/06;H04N5/12;H04N5/268;H04N5/44;H04N5/46;H04N5/74;H04N7/10;H04N9/64 主分类号 G09G5/12
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