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发明名称
半导体积体电路装置及半导体积体电路装置之制造方法
摘要
本发明简化使用双道金属镶嵌(Dual–Damascene)法之多层铜布线之形成步骤。其系将形成于层间绝缘膜45上之光阻膜51作为遮罩,乾式蚀刻层间绝缘膜45,藉由在形成于层间绝缘膜45中途部之停止膜46之表面蚀刻,而形成布线沟52、53。此时,藉由光反射率低之SiCN膜构成停止膜46,藉由使光阻膜51作为曝光时之防反射膜之功能,而无须在光阻膜51之下层形成防反射膜之步骤。
申请公布号
TW200705602
申请公布日期
2007.02.01
申请号
TW095122404
申请日期
2006.06.22
申请人
瑞萨科技股份有限公司
发明人
堀田胜彦;世原乡子
分类号
H01L21/768(2006.01)
主分类号
H01L21/768(2006.01)
代理机构
代理人
陈长文
主权项
地址
日本
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