| 摘要 |
PROBLEM TO BE SOLVED: To provide a technology for attaining improvement in the reading speed, suppressing the increase in memory mat layout areas. SOLUTION: In this semiconductor memory device, by increasing the number of bit line pairs connected with a set of common write data line pairs (7-4, 7-5), the number of write amplifiers (6-10) is reduced. By decreasing the number of bit line pairs (6-3, 6-4) connected with a set of common read data line pairs (7-6, 7-7) and reducing a parasitic capacity connected with the common read data line pairs, time having large potential difference between the common read data line pairs is shortened. This enables shortening of the reading time, while preventing the increase in chip layout areas. COPYRIGHT: (C)2007,JPO&INPIT
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