发明名称 Semiconductor device having multilayer wiring lines and manufacturing method thereof
摘要 A plurality of wiring layers made from a conductive material are formed in the same level layer on a substrate. A plurality of cavity layers are formed in the same level layer as the plurality of wiring layers. The plurality of cavity layers have a cavity ratio which is not smaller than 60%. An interlayer insulating film is formed on the plurality of wiring layers and on the plurality of cavity layers. A barrier metal, an oxygen barrier layer and an insulating layer are formed on side walls of the plurality of wiring layers.
申请公布号 US2007023917(A1) 申请公布日期 2007.02.01
申请号 US20060493928 申请日期 2006.07.27
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 YAMADA MASAKI
分类号 H01L23/48 主分类号 H01L23/48
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