| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an integrated semiconductor structure capable of adjusting the Fermi level of a P-MOS appropriately. <P>SOLUTION: A first transistor region T1 is an n-MOS region, a second transistor region T2 is a p-FET region, a base part dielectric layer 2 made of SiO<SB>2</SB>is formed on the first and second transistor regions, and an N+ polysilicon gate 4 is formed on the dielectric layer 2. The first region is protected by a mask, an aluminum ion is injected, and heat treatment is performed, thus forming a high-dielectric-constant interface dielectric layer 3 of AlxOv between the gate dielectric layer 2 and the N+ polysilicon gate 4, strengthening Fermi pinning effect, and hence adjusting a work function of the P-MOS of N+ polysilicon to a value close to the function of a P+ polysilicon gate. <P>COPYRIGHT: (C)2007,JPO&INPIT |
