| 摘要 |
Double gate transistors ( 12, 13 ) having different bottom gate dielectric thicknesses are formed on a first wafer ( 101 ) by forming a first gate dielectric layer ( 107 ); removing part of the first gate dielectric layer ( 107 ) from a first area ( 60 ); forming a second gate dielectric layer ( 108 ) to obtain a thinner bottom gate dielectric layer ( 150 ) over the first area ( 60 ) and a thicker bottom gate dielectric layer ( 151 ) over the second area ( 70 ); and forming a planar bottom gate layer ( 109 ) over first and second gate dielectric layers. After inverting and bonding the first wafer ( 101 ) to a second wafer ( 103 ), the bottom gate electrodes ( 109 - 2, 109 - 3 ), bottom gate dielectric layers ( 107, 108 ) and channel regions ( 203 - 2, 203 - 3 ) for the first and second double gate transistors ( 12, 13 ) are selectively etched prior to formation of the top gate structures.
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