| 摘要 |
PROBLEM TO BE SOLVED: To reduce current consumption of a voltage regulator in a sleep mode. SOLUTION: In a normal mode, a sub regulator circuit 40 is stopped by a power down signal PDN, and a reference voltage REF outputted from a reference voltage circuit 10 and a monitoring voltage VM generated by voltage division resistors 32, 33 are compared by an operational amplifier 20. A PMOS 31 is controlled by a detection voltage VD of a comparison result, and an internal power source voltage REG is adjusted such that the monitoring voltage VM becomes equal to the reference voltage REF. In the sleep mode, the reference voltage circuit 10 and the operational amplifier 20 are stopped, and the sub regulator circuit 40 is started. A minute current limited by a resistor 43 flows through a PMOS 41 of the sub regulator circuit 40, and a current of the same magnitude is supplied to a PMOS 45 or the like of a threshold voltage output circuit from a PMOS 46 constituting a current mirror. A threshold voltage VT of a node N3 is power-amplified by a voltage follower 47, and is outputted from an output terminal 35. COPYRIGHT: (C)2007,JPO&INPIT
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