| 摘要 |
PROBLEM TO BE SOLVED: To provide an AD converter capable of reducing circuit scale and power consumption. SOLUTION: AΔΣAD converter 1 comprises a sampling part 2 which samples input signal X for each cycle Ts, an AD conversion part 5 which AD converts the input signal X, a DA conversion part 4 which DA converts an output of the AD conversion part 5, and a loop filter 6 which integrates a difference that is provided when an output of the DA conversion part 4 is subtracted from an output of the sampling part 2, which is outputted to the AD conversion part 5. The sampling part 2 comprises two sampling circuits 8a and 8b arranged parallel to each other. The two sampling circuits 8a and 8b operate in staggered manner, so that the sampling circuits 8a and 8b output the input signal X in delayed manner. COPYRIGHT: (C)2007,JPO&INPIT
|
