发明名称 TERNARY MEMORY CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a sense amplifier circuit capable of properly performing readout even when ternary signals of H, M, and L levels are stored in a memory cell by a power supply of 1 V. SOLUTION: The ternary memory circuit is provided with the sense amplifier circuits including: an amplification part amplifying an electric potential of a bit line connected to the memory cell; a first sampling and holding part storing the electric potential amplified by the amplification part in a first capacitor by a first sampling pulse when the bit line is made into a reset electric potential; a second sampling and holding part storing the electric potential amplified by the amplification part in a second capacitor by a second sampling pulse when the bit line is made into a readout electric potential by the memory cell; and a latch circuit detecting and latching the electric potential difference stored in the first and second capacitors, for detecting H and L levels, respectively. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007026672(A) 申请公布日期 2007.02.01
申请号 JP20060298466 申请日期 2006.11.02
申请人 FUJITSU LTD 发明人 KAWASHIMA SHOICHIRO
分类号 G11C11/56 主分类号 G11C11/56
代理机构 代理人
主权项
地址
您可能感兴趣的专利