| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock generation method and a clock generation circuit in which a clock can be generated even if a reception packet containing synchronism time information for clock generation is omitted. <P>SOLUTION: A clock generation circuit comprises: an SYT register 11 to which an SYT contained in each of sequentially received packets is given and which holds and outputs the SYT; a selector 13 to which an estimated time from the reception of a packet before a packet to be received this time to the reception of the packet to be received tis time is given and which uses a correction value thereof and the SYT and outputs the SYT when a complementary SYT is given and it is not notified that the SYT contained in the packet to be received this time is omitted, or outputs a complementary SYT when the omission is notified; and an SYT comparator 15 and a PLL in which a clock with a reference frequency used for receiving a packet is generated using the SYT or the complementary SYT and a cycle time of a bus for transmitting a packet. <P>COPYRIGHT: (C)2007,JPO&INPIT |
