| 摘要 |
PROBLEM TO BE SOLVED: To achieve cost reduction of a data thinning-out circuit by attaining reduction of a circuit scale, power consumption, and a designing period. SOLUTION: Input data DIN are outputted as synchronous data DFF while holding them with a flip-flop 1 synchronously with a clock signal CLK. A thinning-out control circuit 3 outputs a selection control signal SEL, which becomes "Hi" when a count number of the clock signal is coincident with the preset number, and gives it to a selector 2. The selector 2 outputs thinning-out output data DOUT from an output circuit 4 when the selection control signal SEL is "Lo" while outputting the synchronous data DFF when the selection control signal SEL is "Hi". The clock signal CLK serves as a clock frequency used in common by the circuits. Consequently, it is possible to similarly use the clock signal CLK as the clock frequency even if it is composed so as to thin out data with a different thinning-out ratio by providing plural stages of such data thinning-out circuits. COPYRIGHT: (C)2007,JPO&INPIT
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