| 摘要 |
PROBLEM TO BE SOLVED: To minimize bus access time and bus-occupied time to reduce power consumption by dynamically changing allocation of buses to each bus layer of a multilayer bus structure. SOLUTION: The bus 100 is formed of layer buses 101-104 for each layer, and a DMA controller 114, a memory interface part 115 and a bridge 125 are connected thereto. A bus arbiter 105 controls the bus 100. CPUs 111 and 112 are adapted so that connection of input and output buses to the bus 100 is controlled by the bus arbiter 105, and change the bus widths of the input and output buses according to instruction from the bus arbiter 105. The DMA controller 113 is adapted so that connection of the bus of the DMA controller 113 to the bus 100 is also controlled through the bus arbiter 105. COPYRIGHT: (C)2007,JPO&INPIT
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