Test data topology write to memory using latched sense amplifier data and row address scrambling

摘要

For one or more disclosed embodiments, a test data topology may be written to memory by writing data into an initial row of memory cells. The writing of data comprises latching data in a plurality of sense amplifier latches. The initial row of memory cells is deactivated while the latched data is retained in the sense amplifier latches. Another row of memory cells is identified in accordance with a predetermined row addressing sequence for the test data topology. The other row of memory cells is activated to write the retained latched data to the other row.