发明名称 |
Material architecture for the fabrication of low temperature transistor |
摘要 |
A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
|
申请公布号 |
US7169675(B2) |
申请公布日期 |
2007.01.30 |
申请号 |
US20040886442 |
申请日期 |
2004.07.07 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING, LTD |
发明人 |
TAN CHUNG FOONG;LIU JINPING;LEE HYEOKJAE;TEE KHENG CHOK;QUEK ELGIN |
分类号 |
H01L21/336 |
主分类号 |
H01L21/336 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|