发明名称 Power saving refresh scheme for DRAMs with segmented word line architecture
摘要 Techniques and apparatus that may be utilized to reduce current consumption during refresh cycles of DRAM devices that utilize wordline segments are provided. Rather than activate and subsequently de-activate (pre-charge) a master wordline each time a corresponding wordline segment is refreshed, the master wordline may remain activated while corresponding wordline segments are refreshed.
申请公布号 US7170808(B2) 申请公布日期 2007.01.30
申请号 US20050089860 申请日期 2005.03.25
申请人 INFINEON TECHNOLOGIES AG 发明人 HOKENMAIER WOLFGANG
分类号 G11C8/04 主分类号 G11C8/04
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