发明名称 Semiconductor memory device capable of reducing power consumption during reading and standby
摘要 The input data at address 0 is "00000000", including many "0"s. The data at address 0 is inverted to "11111111". At the same time, flag information "1" indicative of inversion is written into the flag bit of the same address 0 . The input data at address 3 also includes many "0"s. Therefore, the data of address 3 is inverted, and flag information "1" is written. The input data at addresses 1 and 2 includes more "1"s than "0"s. Therefore, the data is not inverted, and flag information "0" is written. With regards to the written data, only the data at an address whose flag signal is "1" is inverted again in a reading mode to be eventually read out as a data output signal.
申请公布号 US7170812(B2) 申请公布日期 2007.01.30
申请号 US20050304817 申请日期 2005.12.16
申请人 RENESAS TECHNOLOGY CORP. 发明人 NII KOJI
分类号 G11C5/14;G11C11/41;G11C11/417 主分类号 G11C5/14
代理机构 代理人
主权项
地址