发明名称 Wafer scale integration of electroplated 3D structures using successive lithography, electroplated sacrificial layers, and flip-chip bonding
摘要 Wafer scale fabrication of three dimentional substantially enclosed structures on a MEMS/IC die use a combination of electrodeposition of structural and sacrificial layers and flip-chip alignment and bonding technology. A first wafer contains a die with MEMS and/or IC structures. On this MEMS/IC processed die, a first three dimensional structural component is formed using standard lithographic processes and electrodeposition of a structural layer. A second sacrificial wafer is separately processed using similar lithographic and electrodeposition processes to form a corresponding second three dimensional structural component. The wafers are placed in a flip-chip bonder and aligned. Once aligned, the structural components are bonded together. The bonded wafers are then removed from the bonder and the second sacrificial wafer substrate removed. The resultant die includes a three dimensional structural component with a substantially enclosed cavity as well as MEMS and IC elements.
申请公布号 US7169649(B2) 申请公布日期 2007.01.30
申请号 US20040012597 申请日期 2004.12.16
申请人 PALO ALTO RESEARCH CENTER, INC. 发明人 ROSA MICHEL A.;PEETERS ERIC
分类号 H01L21/56 主分类号 H01L21/56
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