发明名称 Self-testing circuit in semiconductor memory device
摘要 A semiconductor memory device includes a self-testing circuit and a self-redundancy circuit with simple structures. The self-testing circuit includes a comparison circuit which compares write data with read data with respect to normal memory blocks and redundant memory blocks, and a decision circuit which decides if the semiconductor memory device is good or defective based on the plurality of comparison result signals. A signal transfer and holding circuit is connected between the comparison circuit and the decision circuit to transfer the plurality of comparison result signals to the decision circuit and to supply the plurality of comparison result signals to the self-redundancy circuit as a test result.
申请公布号 US7171592(B2) 申请公布日期 2007.01.30
申请号 US20030360862 申请日期 2003.02.10
申请人 FUJITSU LIMITED 发明人 TOGASHI KENJI;HAMADA MORIHIKO;AOKI SHIGEKAZU;SHIGENOBU KATSUMI;SAKA YUKIO;ARISAKA YOSHIKAZU;SAWADA TOYOJI;ASAI TADASHI
分类号 G01R31/28;G06F11/00;G11C29/00;G11C29/12;G11C29/44;H01L21/66;H04B1/74 主分类号 G01R31/28
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