<p>A method for fabricating an NVM(non-volatile memory) cell is provided to minimize the interference effect between adjacent memory cells by forming a spacer in a gate structure including a tungsten pattern such that the spacer includes a middle temperature oxide layer having a lower dielectric constant than that of a nitride layer. A gate structure of a non-volatile memory is formed on a substrate(100), including a tungsten pattern. A middle temperature oxide layer for a spacer is formed on the lateral and upper surfaces of the gate structure and the surface of the substrate by using SH2Cl2 gas and N2O gas, having a lower dielectric constant than that of a nitride layer. A floating gate, a dielectric layer pattern and a control gate including a tungsten pattern are sequentially stacked in the gate structure. A polysilicon layer and a tungsten layer are stacked in the control gate.</p>
申请公布号
KR20070013005(A)
申请公布日期
2007.01.30
申请号
KR20050067307
申请日期
2005.07.25
申请人
SAMSUNG ELECTRONICS CO., LTD.
发明人
YANG, SANG RYOL;SHIN, YU GYUN;HWANG, KI HYUN;NOH, JIN TAE;LIM, JU WAN;AHN, JAE YOUNG;KIM, JIN GYUN;KIM, HONG SUK;LEE, SUNG HAE