发明名称 Semiconductor memories with block-dedicated programmable latency register
摘要 An apparatus and method to delay output of data from different regions of a memory device in response to a read enable signal, the delaying of the output of data is based on the location of the regions of the memory device with respect to an output circuit that receives the data, wherein the different regions of the memory device have different CAS latency values dedicated to each region to set the delay time of each region of the memory device.
申请公布号 US2007019481(A1) 申请公布日期 2007.01.25
申请号 US20060407024 申请日期 2006.04.20
申请人 PARK CHUL W 发明人 PARK CHUL W.
分类号 G11C7/00 主分类号 G11C7/00
代理机构 代理人
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