发明名称 Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules
摘要 A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while providing a common electrical ground for both voltage domains. The integrated circuit chip may be a microprocessor having a nominal operating voltage, and the different voltages of the two voltage domains are both within the tolerance range of the nominal operating voltage but one of the voltage domains is aligned with a high power density area of the microprocessor (e.g., the microprocessor core) and provides a slightly greater voltage. The higher power voltage domain preferably has a ratio of voltage pins to ground pins that is greater than one.
申请公布号 US2007022398(A1) 申请公布日期 2007.01.25
申请号 US20050184350 申请日期 2005.07.19
申请人 发明人 HARIDASS ANAND;HUBER ANDREAS;KLINK ERICH;STRACH THOMAS;SUPPER JOCHEN
分类号 G06F17/50;H01L21/00 主分类号 G06F17/50
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