发明名称 |
Wafer-level-chip-scale package and method of fabrication |
摘要 |
A wafer-level-chip-scale package and related method of fabrication are disclosed. The wafer-level-chip-scale package comprises a semiconductor substrate comprising an integrated circuit, a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit, and a protective portion formed from an insulating material and disposed on bottom and side surfaces of the semiconductor substrate.
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申请公布号 |
US2007018324(A1) |
申请公布日期 |
2007.01.25 |
申请号 |
US20060444410 |
申请日期 |
2006.06.01 |
申请人 |
KWON YONG-HWAN;LEE CHUNG-SUN;KANG WOON-BYUNG |
发明人 |
KWON YONG-HWAN;LEE CHUNG-SUN;KANG WOON-BYUNG |
分类号 |
H01L23/48 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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