| 摘要 |
A distributed, hierarchically-structured, programmable priority encoder for a content addressable memory (CAM) device including at least one section, the section further including a section level priority encoder, and a plurality of blocks, each block further including a block level priority encoder, and a plurality of slices. The distributed, hierarchically-structured, programmable priority encoder, wherein each slice further including a CAM slice, a maskable comparand register coupled to the CAM slice and a programmable priority encoder coupled to said CAM slice and further coupled to said block level priority encoder.
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