发明名称 MULTIPLE DATA RATE IN SERIAL INTERFACE FOR PROGRAMMABLE LOGIC DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a serial interface capable of responding suitably to a wide range data rate. SOLUTION: A serial interface for a PLD (20) supports a wide range of the data rate by providing the first number of channels (21-24) for supporting the data rate of the first range and the second number of channels (200) for supporting the second range of the data rate. The data rate for the first range is lower than the data rate for the second range. The first number of the channels is larger than the number of the second channels which is preferably one. The number of the first channels in each of the interfaces is suitably four. Each of the channels includes a physical medium connection module (26) and a physically coded sublayer module (25). Each of the high-speed channels for the channels of the second number includes a clock management unit. The low-speed channel of the channel of the first number shares one or more clock management units. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007018498(A) 申请公布日期 2007.01.25
申请号 JP20060086647 申请日期 2006.03.27
申请人 ALTERA CORP 发明人 VENKATA RAMANAND;PATEL RAKESH H;LEE CHONG H
分类号 G06F13/38;G06F3/00;H04L13/08;H04L29/08 主分类号 G06F13/38
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