| 摘要 |
PROBLEM TO BE SOLVED: To provide a microprocessor, of a simple structure, which is capable of reducing time for designing and verifying, and protecting tasks which do not cause bus errors while executing a plurality of tasks. SOLUTION: The microprocessor comprises: a command fetch unit 16 which is provided with a first request queue device 8 for requesting a bus request caused by a command fetch of a bus interface unit 4 and storing incomplete requests out of the command fetch requests outputted to the bus interface unit 4; a load/store unit 3 for requesting a bus request caused by a load command or store command of the bus interface unit; a decode unit 1 for decoding commands from the command fetch unit 16; an execution unit 2 for executing commands from the decode unit 1; and an OR/unit 10 for activating an output signal when any input signal from either the decode unit 1, the performance unit 2, or load/store unit 3 becomes active to input it to the command fetch unit 16. COPYRIGHT: (C)2007,JPO&INPIT
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