| 摘要 |
PROBLEM TO BE SOLVED: To provide a data processor capable of performing efficiently interruption processing in both directions among a plurality of controllers with simple constitution. SOLUTION: In a complex device 10, a controller 100 has a register 110 including a plurality of interruption request domains assigned to each interruption request destination, output terminals 122a-122d connected to each interruption request destination trough signal wires 156a-156d, and an interruption signal output part 120 for outputting an interruption signal to the corresponding interruption request destination through the output terminal following writing through a bus 150 of an interruption signal generation request to the interruption request domain, and each controller 300-500 is equipped with memories 310-510 for storing interruption information, and PCIC's 306-506 for writing through the bus 150 of the interruption information in the memories 310-510 of the interruption request destination and the interruption signal generation request in the interruption request domain corresponding to the interruption request destination in the register 110 when performing interruption processing. COPYRIGHT: (C)2007,JPO&INPIT
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