| 摘要 |
<P>PROBLEM TO BE SOLVED: To make a modular chip selection control circuit scalable by letting the modular chip selection control circuit have an address decode stage with a first number of address decoders, a control stage with a second number of control units, and a pin configuration stage with a third number of pin configuration logic circuits. <P>SOLUTION: The number of memory regions, the access pipeline depth, and the number of chip selection signals are independent respectively, and may be changed with reference to chip designs. The control stage includes an early pipeline control circuit which allows the control units to pipeline pending memory cycles, based on an accessed region's characteristics. The early pipeline control circuit together with the control units enforces a set of pipelining rules to ensure data integrity and proper cycle termination, thus providing an efficient series of pipelined memory access cycles. <P>COPYRIGHT: (C)2007,JPO&INPIT |
