| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL frequency synthesizer, a semiconductor integrated circuit, and a communication device which allow the reduction in power consumption and have high stability of operations. <P>SOLUTION: In the PLL frequency synthesizer, a variable frequency divider comprises a plurality of stages of D-FFs 21, 22, and 23. In the D-FF 21, bias currents I1 and I3 flow by transistors Tr1 and Tr3 when switch circuits SW1 to SW5 are in an off-state, and bias currents I1 to I4 flow by transistors Tr1 to Tr4 when switch circuits SW1 to SW5 are in an on-state. Voltage amplitudes of signals outputted from a Q terminal 36 and a QX terminal 37 are always (Ibias×RL)/2. Consequently, the power consumption of the variable frequency divider can be reduced. <P>COPYRIGHT: (C)2007,JPO&INPIT |
