| 摘要 |
The present invention concerns a phase Detector for detecting a phase difference between a data clock DATA-CLK and a reference clock REF-CLK using a data signal DATA. A transition of the data signal DATA is synchronous with a transition of the data clock DATA-CLK. The data clock DATA-CLK and the reference clock REF-CLK have the same frequency. The phase detector comprises a first signal generator ( 42 ) for generating a first binary signal ERRQ, a pulse width of which is equal to a first time difference DeltaT 1 between a transition of the data signal DATA and a transition of a first reference clock signal CKQ adjacent to the transition of the data signal DATA, wherein the first signal generator comprises an input for receiving the first reference clock signal CKQ and an input for receiving the data signal DATA. The phase detector comprises a second signal generator ( 40 ) for generating a second binary signal ERRI. The pulse width of the second binary signal ERRI is equal to a second time difference DeltaT 2 between a transition of the data signal DATA and a transition of the second reference clock signal CKI adjacent to the transition of the data signal DATA, wherein the second signal generator ( 40 ) comprises an input for receiving the second binary signal ERRI and an input for receiving the second reference signal CKI. The phase detector comprises an output signal generator ( 40 ) for generating an output signal representative of the phase difference between the data clock DATA-CLK and the reference clock REF-CLK, wherein the output signal is equal to ERRQ-2*(ERRQ AND ERRI) and AND represents a logical AND-operation or the output is equal to (ERRQ XOR ERRI)-ERRI, wherein XOR represents a logical XOR-operation.
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