发明名称 |
Controlling system for gate formation of semiconductor devices |
摘要 |
A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.
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申请公布号 |
US2007020777(A1) |
申请公布日期 |
2007.01.25 |
申请号 |
US20050188324 |
申请日期 |
2005.07.25 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
TSO CHIA-TSUNG;LAI JIUN-HONG;WU MEI-JEN;HSU LI T.;SU PIN C.;CHEN PO-ZEN |
分类号 |
H01L21/66;H01L21/302;H01L21/76 |
主分类号 |
H01L21/66 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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