| 摘要 |
<p>The present invention relates to an asynchronous data buffer for transferring m data elements of a burst-transfer between two asynchronous systems. The asynchronous data buffer comprises a data memory (112) for storing m data elements of a data burst and a valid bit memory (114) for storing m input valid bits corresponding to the m data elements. Input control logic circuitry (116) generates the m input valid bits and controls storage of the same and the m data elements. After storage of the m input valid bits an input control signal is provided for inverting the input valid bits of a following data burst. Therefore, after each burst-transfer of m data elements the input valid bit is inverted, automatically rendering all data elements of a previous burst-transfer invalid.</p> |
