| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an image compressing circuit, etc., capable of reducing the load of a host CPU. <P>SOLUTION: This LCD controller LSI 1 comprises a resize processing circuit 2, a shutter processing circuit 3, a JPEG encoding module 4, a FIFO buffer 5 and a host interface 6. The JPEG encoding module 4 comprises a JPEG encoding processing circuit 7 and a control circuit 8. The control circuit 8 comprises a register group 21 and a control processing part 22. When the control circuit 8 receives from the host CPU 51 an instruction to the effect that moving image data are started to be compressed, the control circuit 8 controls the shutter processing circuit 3 so as to obtain moving image data supplied from a CCD camera 54 and controls the JPEG encoding processing circuit 7 so as to apply image compression processing to the moving image data obtained by the shutter processing circuit 3. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
