发明名称 METHODS AND APPARATUS FOR MULTI-PROCESSOR PIPELINE PARALLELISM
摘要 A processor is provided which has a modular organization including at least one local store operable to store data and instructions for execution, at least one functional unit operable to execute instructions on data provided from the local store, and at least one issue logic unit operable to convert instructions provided from the local store into operations of the functional unit for executing the instructions. Each such issue logic unit is operable to control execution of the instruction by one or more functional units according to a common instruction set. ® KIPO & WIPO 2007
申请公布号 KR20070011468(A) 申请公布日期 2007.01.24
申请号 KR20067023556 申请日期 2006.11.10
申请人 SONY COMPUTER ENTERTAINMENT INC. 发明人 YAMAZAKI TAKESHI
分类号 G06F9/38;G06F9/318;G06F9/46;G06F15/00;G06F17/50 主分类号 G06F9/38
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