| 摘要 |
A delay locked loop circuit, a semiconductor memory apparatus having the same, and a method for synchronizing a clock of a semiconductor memory apparatus are provided to reduce power consumption when a semiconductor memory apparatus is operated in a standby mode of a power down mode or a self refresh mode by having a variable voltage source. A delay locked loop circuit includes a variable voltage source(2000), and a delay locked loop(1000). The variable voltage source(2000) generates a variable bias voltage having a different amplitude according to an operation mode in response to a standby signal. The delay locked loop(1000) generates an internal clock signal synchronized to an external clock signal in response to the variable bias voltage and the standby signal. The variable voltage source(2000) includes a reference voltage generation unit and a driving unit. The reference voltage generation unit generates a reference voltage signal. The driving unit generates the variable bias voltage having the different amplitude according to the operation mode in response to the standby signal and the reference voltage signal.
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