SEMICONDUCTOR MEMORY DEVICE USING PIPELINED-BUFFER PROGRAMMING SCHEME

摘要

A semiconductor memory device using a pipelined-buffer programming scheme is provided to minimize noise proportional to the number of sense amplifiers by reducing the increase of the layout area. A cell array(110) includes a plurality of memory cells. A write driver includes a plurality of write units. Each of the write units programs each of the memory cells. A sense amplifier includes a plurality of read units. Each of read units senses each of the memory cells in a program verification operation. A selection circuit selects the write units or the read units in order to program or sense the memory cells in response to a column address. A data input unit provides program data to the selected write unit while a program is operated. The data input unit receives verification data from the selected read unit while a program verification operation is performed.